1. Field of the Invention
2. Description of the Prior Art
Great progress has been made in the manufacture of Dynamic Random Access Memory (DRAM) using high density integrated circuit technology. The industry has progressed from DRAMs of 16 Kbits capacity to DRAMs of up to 64 Mbits capacity.
A memory cell for each bit in semiconductor DRAM typically consists of a storage capacitor and an access transistor. Either the source or drain of the transistor is connected to one terminal of the capacitor. The other side of the transistor and the transistor gate electrode are connected to external connection lines called a bit line and a word line, respectively. The other terminal of the capacitor is connected to a reference voltage. Thus, the formation of a DRAM memory cell comprises the formation of a transistor, a capacitor and contacts to external circuits. The capacitor type that is most typically used in DRAM memory cells are planar capacitors, which are relatively simple to manufacture.
However, in order to achieve high performance (i.e. high density), memory cells in DRAM technology must be scaled down to the submicrometer range. Thus, as the capacity of DRAMs has increased, the size of the memory cells must steadily decrease. For very small memory cells, planar capacitors become very difficult to use reliably. Specifically, as the size of the capacitor decreases, then the capacitance of the capacitor also decreases. Similarly, the size of the charge capable of being stored by the capacitor decreases. This results in the capacitor being very susceptible to a particle interference. Additionally, as the capacitance decreases, the charge held by storge capacitor must be refreshed often.
Prior art approaches to overcoming these problems have resulted in the development of the trench capacitor (see U.S. Pat. No. 5,374,580) and the stacked capacitor. The trench capacitor has the well-known problem of "gated diode leakage," which is the leakage of current resulting in the trench capacitor failing to hold a charge. The stacked capacitor suffers from the problem of high manufacturing complexity.
Another way to increase the capacitance per unit area is to etch a groove in the capacitor terminal, thus increasing the area of the capacitor. See, for example, U.S. Pat. No. 4,225,945 and U.S. Pat. No. 5,374,580. Reducing the thickness of the dielectric also can improve the capacitance of the capacitor, but this approach is limited because of yield and reliability problems.
The present invention provides a DRAM capacitor which provides high storage capacitance per unit of semiconductor surface.